#include "hw/esp8266.h" // https://github.com/pvvx/esp8266web/blob/master/include/hw/esp8266.h
#define i2c_bbpll 0x67 // 103
#define i2c_bbpll_en_audio_clock_out 4
#define i2c_bbpll_en_audio_clock_out_msb 7
#define i2c_bbpll_en_audio_clock_out_lsb 7
#define i2c_bbpll_hostid 4
#define i2c_saradc 0x6C // 108
#define i2c_saradc_hostid 2
#define i2c_saradc_en_test 0
#define i2c_saradc_en_test_msb 5
#define i2c_saradc_en_test_lsb 5
#define i2c_writeReg_Mask(block, host_id, reg_add, Msb, Lsb, indata) \
rom_i2c_writeReg_Mask(block, host_id, reg_add, Msb, Lsb, indata)
#define i2c_readReg_Mask(block, host_id, reg_add, Msb, Lsb) \
rom_i2c_readReg_Mask(block, host_id, reg_add, Msb, Lsb)
#define i2c_writeReg_Mask_def(block, reg_add, indata) \
i2c_writeReg_Mask(block, block##_hostid, reg_add, reg_add##_msb, reg_add##_lsb, indata)
#define i2c_readReg_Mask_def(block, reg_add) \
i2c_readReg_Mask(block, block##_hostid, reg_add, reg_add##_msb, reg_add##_lsb)
//---- Init CPU
IO_RTC_4 = 0; // отключить WiFi // 0x60000710 = 0
GPIO0_MUX = 0; // отключить вывод Q_CLK
// CLK CPU 160 MHz
rom_i2c_writeReg(103, 4, 1, 136);
rom_i2c_writeReg(103, 4, 2, 145);
CLK_PRE_PORT |= 1;
ets_update_cpu_frequency(80 * 2);
...
//---- Init SAR
IO_RTC_4 |= 0x06000000; // переключить источник тактирования (частоту) для SAR SET_PERI_REG_MASK(0x60000710,0x6000000);
i2c_writeReg_Mask(108,2,0,4,4,1);
i2c_writeReg_Mask(108,2,1,1,0,2);
i2c_writeReg_Mask(98,1,3,7,4,15);
DPORT_BASE[0x18>>2] |= 0x038f0000; // SET_PERI_REG_MASK(0x3FF00018,0x038f0000);
HDRF_BASE[0x0e8>>2] |= 0x01800000; // SET_PERI_REG_MASK(0x600005e8,0x01800000);
// включить SAR
i2c_writeReg_Mask_def(i2c_saradc, i2c_saradc_en_test, 1); //select test mux
SAR_CFG1 |= 1 << 21;
// ожидание готовности SAR
while((SAR_CFG >> 24) & 0x07);
....
// user code