ESP8266 UART REG

UART REG release 18.11.2014

AddressRegNameSignalBitPosDefaultSW(R/W)Description
0x0UART_FIFO[31:8]24'h0ROUART FIFO,length 128
rxfifo_rd_byte[7:0]8'b0ROR/W share the same address
0x4UART_INT_RAWUART_INT_RAWUART INTERRUPT RAW STATE
rxfifo_tout_int_raw[8]1'b0ROThe interrupt raw bit for Rx time-out interrupt(depands on the UART_RX_TOUT_THRHD)
brk_det_int_raw[7]1'b0ROThe interrupt raw bit for Rx byte start error
cts_chg_int_raw[6]1'b0ROThe interrupt raw bit for CTS changing level
dsr_chg_int_raw[5]1'b0ROThe interrupt raw bit for DSR changing level
rxfifo_ovf_int_raw[4]1'b0ROThe interrupt raw bit for rx fifo overflow
frm_err_int_raw[3]1'b0ROThe interrupt raw bit for other rx error
parity_err_int_raw[2]1'b0ROThe interrupt raw bit for parity check error
txfifo_empty_int_raw[1]1'b0ROThe interrupt raw bit for tx fifo empty interrupt(depands on UART_TXFIFO_EMPTY_THRHD bits)
rxfifo_full_int_raw[0]1'b0ROThe interrupt raw bit for rx fifo full interrupt(depands on UART_RXFIFO_FULL_THRHD bits)
0x8UART_INT_STUART_INT_STUART INTERRUPT STATE REGISTER?UART_INT_RAW&UART_INT_ENA?
rxfifo_tout_int_st[8]1'b0ROThe interrupt state bit for Rx time-out event
brk_det_int_st[7]1'b0ROThe interrupt state bit for rx byte start error
cts_chg_int_st[6]1'b0ROThe interrupt state bit for CTS changing level
dsr_chg_int_st[5]1'b0ROThe interrupt state bit for DSR changing level
rxfifo_ovf_int_st[4]1'b0ROThe interrupt state bit for RX fifo overflow
frm_err_int_st[3]1'b0ROThe interrupt state for other rx error
parity_err_int_st[2]1'b0ROThe interrupt state bit for rx parity error
txfifo_empty_int_st[1]1'b0ROThe interrupt state bit for TX fifo empty
rxfifo_full_int_st[0]1'b0ROThe interrupt state bit for RX fifo full event
0xCUART_INT_ENAUART_INT_ENAUART INTERRUPT ENABLE REGISTER
rxfifo_tout_int_ena[8]1'b0R/WThe interrupt enable bit for rx time-out interrupt
brk_det_int_ena[7]1'b0R/WThe interrupt enable bit for rx byte start error
cts_chg_int_ena[6]1'b0R/WThe interrupt enable bit for CTS changing level
dsr_chg_int_ena[5]1'b0R/WThe interrupt enable bit for DSR changing level
rxfifo_ovf_int_ena[4]1'b0R/WThe interrupt enable bit for rx fifo overflow
frm_err_int_ena[3]1'b0R/WThe interrupt enable bit for other rx error
parity_err_int_ena[2]1'b0R/WThe interrupt enable bit for parity error
txfifo_empty_int_ena[1]1'b0R/WThe interrupt enable bit for tx fifo empty event
rxfifo_full_int_ena[0]1'b0R/WThe interrupt enable bit for rx fifo full event
0x10UART_INT_CLRUART_INT_CLRUART INTERRUPT CLEAR REGISTER
rxfifo_tout_int_clr[8]1'b0WOSet this bit to clear the rx time-out interrupt
brk_det_int_clr[7]1'b0WOSet this bit to clear the rx byte start interrupt
cts_chg_int_clr[6]1'b0WOSet this bit to clear the CTS changing interrupt
dsr_chg_int_clr[5]1'b0WOSet this bit to clear the DSR changing interrupt
rxfifo_ovf_int_clr[4]1'b0WOSet this bit to clear the rx fifo over-flow interrupt
frm_err_int_clr[3]1'b0WOSet this bit to clear other rx error interrupt
parity_err_int_clr[2]1'b0WOSet this bit to clear the parity error interrupt
txfifo_empty_int_clr[1]1'b0WOSet this bit to clear the tx fifo empty interrupt
rxfifo_full_int_clr[0]1'b0WOSet this bit to clear the rx fifo full interrupt
0x14UART_CLKDIVUART_CLKDIVUART CLK DIV REGISTER
uart_clkdiv[19:0]20'h2B6R/WBAUDRATE = UART_CLK_FREQ / UART_CLKDIV
0x18UART_AUTOBAUDUART_AUTOBAUDUART BAUDRATE DETECT REGISTER
glitch_filt[15:8]8'h10R/W
[7:1]7'h0RO
autobaud_en[0]1'b0R/WSet this bit to enable baudrate detect
UART_STATUSUART_STATUSUART_STATUSUART STATUS REGISTER
txd[31]8'h0ROThe level of the uart txd pin
rtsn[30]1'b0ROThe level of uart rts pin
dtrn[29]1'b0ROThe level of uart dtr pin
[28:14]5'b0RO
txfifo_cnt[23:16]8'b0RONumber of data in UART TX fifo
rxd[15]1'b0ROThe level of uart rxd pin
ctsn[14]1'b0ROThe level of uart cts pin
dsrn[13]1'b0ROThe level of uart dsr pin
[12:8]5'b0RO
rxfifo_cnt[7:0]8'b0RONumber of data in uart rx fifo
0x20UART_CONF0UART_CONF0UART CONFIG0(UART0 and UART1)
uart_dtr_inv[24]1'h0R/WSet this bit to inverse uart dtr level
uart_rts_inv[23]1'h0R/WSet this bit to inverse uart rts level
uart_txd_inv[22]1'h0R/WSet this bit to inverse uart txd level
uart_dsr_inv[21]1'h0R/WSet this bit to inverse uart dsr level
uart_cts_inv[20]1'h0R/WSet this bit to inverse uart cts level
uart_rxd_inv[19]1'h0R/WSet this bit to inverse uart rxd level
txfifo_rst[18]1'h0R/WSet this bit to reset uart tx fifo
rxfifo_rst[17]1'h0R/WSet this bit to reset uart rx fifo
tx_flow_en[15]1'b0R/WSet this bit to enable uart tx hardware flow control
uart_loopback[14]1'b0R/WSet this bit to enable uart loopback test mode
txd_brk[8]1'b0R/WRESERVED, DO NOT CHANGE THIS BIT
sw_dtr[7]1'b0R/Wsw dtr
sw_rts[6]1'b0R/Wsw rts
stop_bit_num[5:4]2'd1R/WSet stop bit: 1:1bit 2:1.5bits 3:2bits
bit_num[3:2]2'd3R/WSet bit num: 0:5bits 1:6bits 2:7bits 3:8bits
parity_en[1]1'b0R/WSet this bit to enable uart parity check
parity[0]1'b0R/WSet parity check: 0:even 1:odd
UART_CONF1UART CONFIG1
0x24UART_CONF1rx_tout_en[31]1'b0R/WSet this bit to enable rx time-out function
rx_tout_thrhd[30:24]7'b0R/WConfig bits for rx time-out threshold,uint: byte,0-127
rx_flow_en[23]1'b0R/WSet this bit to enable rx hardware flow control
rx_flow_thrhd[22:16]7'h0R/WThe config bits for rx flow control threshold,0-127
[15]1'b0RO
txfifo_empty_thrhd[14:8]7'h60R/WThe config bits for tx fifo empty threshold,0-127
[7]1'b0RO
rxfifo_full_thrhd[6:0]7'h60R/WThe config bits for rx fifo full threshold,0-127
0x28UART_LOWPULSEUART_LOWPULSE
lowpulse_min_cnt[19:0]20'hFFFFFROused in baudrate detect
0x2CUART_HIGHPULSEUART_HIGHPULSE
highpulse_min_cnt[19:0]20'hFFFFFROused in baudrate detect
0x30UART_RXD_CNT
rxd_edge_cnt[9:0]10'h0ROused in baudrate detect
0x78UART_DATEuart_date[31:0]32'h062000R/WUART HW INFO
0x7CUART_IDuart_id[31:0]32'h0500R/W

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