void my_app_adc_init_test(bool shorted)
{
///Step 1: power off sar adc/////////////////////////////////////////////////////////
/******power off sar adc********/
adc_power_on_sar_adc(0);
//////////////////////////////////////////////////////////////////////////////////////
////Step 2: Config some common adc settings(user can not change these)/////////////////
/******enable signal of 24M clock to sar adc********/
adc_enable_clk_24m_to_sar_adc(1);
/******set adc sample clk as 4MHz******/
adc_set_sample_clk(5); //adc sample clk= 24M/(1+5)=4M
/******set adc L R channel Gain Stage bias current trimming******/
adc_set_left_gain_bias(GAIN_STAGE_BIAS_PER100);
adc_set_right_gain_bias(GAIN_STAGE_BIAS_PER100);
adc_set_chn_enable_and_max_state_cnt(ADC_MISC_CHN|ADC_LEFT_CHN, 4); //set total length for sampling state machine and channel
adc_set_state_length(240, 240, 10); //set R_max_mc,R_max_c,R_max_s // 500 100
gpio_set_func(GPIO_PB7, AS_GPIO);
gpio_set_input_en(GPIO_PB7, 0);
gpio_set_output_en(GPIO_PB7, 0);
gpio_write(GPIO_PB7, 0);
gpio_set_func(GPIO_PB6, AS_GPIO);
gpio_set_input_en(GPIO_PB6, 0);
gpio_set_output_en(GPIO_PB6, 0);
gpio_write(GPIO_PB6, 0);
if (shorted) //закороченные входы
{
adc_set_ain_channel_differential_mode(ADC_MISC_CHN, B7P, B7N);
}
else
{
adc_set_ain_channel_differential_mode(ADC_MISC_CHN, B7P, B6N /*B7P, B6N*/);
}
//set misc channel resolution 14 bit
//notice that: in differential_mode MSB is sign bit, rest are data, here BIT(13) is sign bit
adc_set_resolution(ADC_MISC_CHN, RES14); //set resolution
//set misc channel vref 1.2V
adc_set_ref_voltage(ADC_MISC_CHN, ADC_VREF_1P2V ); //set channel Vref
//set misc t_sample 6 cycle of adc clock: 6 * 1/4M
adc_set_tsample_cycle(ADC_MISC_CHN, SAMPLING_CYCLES_6); //Number of ADC clock cycles in sampling phase
//set Analog input pre-scaling 1/8
adc_set_ain_pre_scaler(ADC_PRESCALER_1F8);
adc_config_misc_channel_buf((unsigned short *)adc_data_buf, ADC_SAMPLE_NUM<<2); //size: ADC_SAMPLE_NUM*4
dfifo_enable_dfifo2();
// left channel:
AudioRate_Typedef Audio_Rate=AUDIO_16K;
audio_config_mic_buf ( buffer_mic, TL_MIC_BUFFER_SIZE);
gpio_set_output_en(GPIO_AMIC_SP, 0);
gpio_set_output_en(GPIO_AMIC_SN, 0);
adc_set_input_mode(ADC_LEFT_CHN, DIFFERENTIAL_MODE); //left channel differential mode
adc_set_ain_channel_differential_mode(ADC_LEFT_CHN, PGA0P, PGA0N); //left channel positive and negative data in
//adc_set_ref_voltage(ADC_LEFT_CHN, ADC_VREF_0P6V); // одинаковые должны быть
adc_set_resolution(ADC_LEFT_CHN, RES14); //left channel resolution
adc_set_tsample_cycle(ADC_LEFT_CHN, SAMPLING_CYCLES_6); //left channel tsample
// adc_set_vref_vbat_divider(ADC_VBAT_DIVIDER_OFF); //vbat vref divider
// adc_set_ain_pre_scaler(ADC_PRESCALER_1); //ain pre scaler none
// adc_set_itrim_preamp(ADC_CUR_TRIM_PER75);
// adc_set_itrim_vrefbuf(ADC_CUR_TRIM_PER100);
// adc_set_itrim_vcmbuf(ADC_CUR_TRIM_PER100);
//PGA0 left C0/C1 ON,
//PGA1 right C2/C3 OFF
SET_PGA_LEFT_P_AIN(PGA_AIN_C1);
SET_PGA_LEFT_N_AIN(PGA_AIN_C1);
SET_PGA_RIGHT_P_AIN(PGA_AIN_C0);
SET_PGA_RIGHT_N_AIN(PGA_AIN_C0);
//
adc_set_left_boost_bias(GAIN_STAGE_BIAS_PER75);
analog_write (areg_adc_pga_ctrl, MASK_VAL( FLD_PGA_ITRIM_GAIN_L, GAIN_STAGE_BIAS_PER150, \
FLD_PGA_ITRIM_GAIN_R,GAIN_STAGE_BIAS_PER150, \
FLD_ADC_MODE, 0, \
FLD_SAR_ADC_POWER_DOWN, 1, \
FLD_POWER_DOWN_PGA_CHN_L, 0, \
FLD_POWER_DOWN_PGA_CHN_R, 1) );
WriteAnalogReg(0xfe,0x05); //0x80+126 = 0x05,0xfe default value is 0xe5,for output audio, must clear 0xfe<7:5>
/////////////////////////////// PGA gain setting ///////////////////////////////////////
//0xb63[7] 1b'1 enable gain mode to manual mode manual mode 1
reg_pga_fix_value = MASK_VAL( FLD_PGA_POST_AMPLIFIER_GAIN,PGA_POST_GAIN_12DB,\
FLD_PGA_PRE_AMPLIFIER_GAIN,PGA_PRE_GAIN_38DB,\
FLD_PGA_GAIN_FIX_EN, 1);
////////////////////////////// ALC HPF LPF setting /////////////////////////////////
//enable hpf, enable lpf, anable alc, disable double_down_sampling
reg_aud_alc_hpf_lpf_ctrl = MASK_VAL( FLD_AUD_IN_HPF_SFT, 0x07, //different pcb may set different value. 5
FLD_AUD_IN_HPF_BYPASS, 0, \
FLD_AUD_IN_ALC_BYPASS, 1, \
FLD_AUD_IN_LPF_BYPASS, 1, \
FLD_DOUBLE_DOWN_SAMPLING_ON,\
(Audio_Rate==AUDIO_32K)?0:1);
if(Audio_Rate==AUDIO_32K)
{
reg_dfifo_dec_ratio = AMIC_CIC_Rate[AUDIO_32K];
}
else
{
if(Audio_Rate==AUDIO_16K)
{
reg_dfifo_dec_ratio = AMIC_CIC_Rate[AUDIO_32K];//32k
}
else if(Audio_Rate==AUDIO_8K)
{
reg_dfifo_dec_ratio = AMIC_CIC_Rate[AUDIO_16K];//16k
}
}
//alc mode select digital mode
reg_aud_alc_cfg &= ~FLD_AUD_ALC_ANALOG_MODE_EN;
//alc left channel select manual regulate, and set volume //0x28
reg_aud_alc_vol_l_chn = MASK_VAL( FLD_AUD_ALC_MIN_VOLUME_IN_DIGITAL_MODE, 0x8, \
FLD_AUD_ALC_DIGITAL_MODE_AUTO_REGULATE_EN, 0);
//2. Dfifo setting
reg_clk_en2 |= FLD_CLK2_DFIFO_EN; //enable dfifo clock, this will be initialed in cpu_wakeup_int()
#if AUDIO_DBL_BUF_ENABLE
reg_dfifo_mode = FLD_AUD_DFIFO1_IN;
#else
reg_dfifo_mode |= FLD_AUD_DFIFO0_IN;
#endif
//amic input, mono mode, enable decimation filter
reg_dfifo_ain = MASK_VAL( FLD_AUD_DMIC0_DATA_IN_RISING_EDGE,AUDIO_DMIC_DATA_IN_FALLING_EDGE,\
FLD_AUD_INPUT_SELECT, AUDIO_INPUT_AMIC, \
FLD_AUD_INPUT_MONO_MODE, 1, \
FLD_AUD_DECIMATION_FILTER_BYPASS, 1);
reg_audio_dec_mode |= FLD_AUD_LNR_VALID_SEL | FLD_AUD_CIC_MODE;
adc_power_on_sar_adc(1);
}
/////////////////////////////////////////////////// end test //////////////////////////////////////////////////////////////////
