Возможно, но это уровнем ниже. Нужно что задает загрузчик и расшифровка процедур из ld\eagle.rom.addr.v6.ld
Остальное задается в трансляторе си. Типа:
Configuration Overview
Core Name lx106
Core Description 106Micro with large local memory
Configuration Detail
TIE source(s) for configuration
Xtensa ISA version LX3.0
Instruction options
16-bit MAC with 40 bit Accumulator no
MUL16 yes
MUL32 Iterative
32 bit integer divider no
Single Precision FP (coprocessor id 0) no
Double Precision FP Accelerator no
CLAMPS no
NSA/NSAU yes
MIN/MAX and MINU/MAXU no
SEXT no
Boolean Registers no
Number of Coprocessors (NCP) 0
Enable Density Instructions yes
Enable Processor ID yes
Zero-overhead loop instructions no
Synchronize instruction no
Conditional store synchronize instruction no
TIE arbitrary byte enables no
Count of Load/Store units 1
Max instruction width (bytes) 3
L32R hardware support Extended L32R
Pipeline length 5
FLIX3: 3-way FLIX no
Vectra LX DSP coprocessor instruction family no
VectraVMB: Extra DSP Instructions no
ConnX D2 DSP no
HiFi2 Audio Engine DSP coprocessor instruction family no
Thread Pointer no
GPIO32: 32-bit GPIO interface no
QIF32: 32-bit Queue Interface no
Interrupts enabled ? yes
Interrupt count 15
Int 0 type / priority level ExtLevel / 1
Int 1 type / priority level ExtLevel / 1
Int 2 type / priority level ExtLevel / 1
Int 3 type / priority level ExtLevel / 1
Int 4 type / priority level ExtLevel / 1
Int 5 type / priority level ExtLevel / 1
Int 6 type / priority level Timer / 1
Int 7 type / priority level Software / 1
Int 8 type / priority level ExtEdge / 1
Int 9 type / priority level ExtEdge / 1
Int 10 type / priority level ExtEdge / 1
Int 11 type / priority level ExtEdge / 1
Int 12 type / priority level ExtEdge / 1
Int 13 type / priority level ExtEdge / 1
Int 14 type / priority level NMI / 3
High Priority Interrupts yes
Interrupt Level count 2
Medium Level Interrupts no
Timer count yes
Timer count 1
Timer 0 6
Byte ordering (endianness) Little Endian
Address registers available for call windows 16
Miscellaneous Special Register count 0
Generate exception on unaligned load/store address exception
Enable Processor Interface (PIF) yes
Write buffer entries 1
Enable PIF Write Responses no
Prioritize Load Before Store no
Widths of Cache and Memory Interfaces
Width of Instruction Fetch Interface 32
Width of Data Memory/Cache interface 32
Width of PIF interface 32
Width of Interface to instruction cache 0
Instruction Cache Not Selected
Data Cache Not Selected
Debug yes
Data address breakpoint registers 1
Instruction address breakpoint registers 1
Debug interrupt level 2
Trace port (address trace and pipeline status) yes
Add data trace no
On Chip Debug(OCD) yes
Use array of 4 Debug Instruction Registers (DIRs) no
External Debug Interrupt yes
Full scan yes
Make latches transparent no
Xtensa Exception Architecture XEA2
Memory Protection/MMU Region Protection
System RAM start address / size 0x60000000 / 64M
System ROM start address / size 0x50000000 / 16M
Local Memory
Instruction RAM [0] start address / size 0x40000000 / 1M [busy]
Instruction RAM [1] start address / size 0x40100000 / 1M [busy]
Instruction ROM start address / size 0x40200000 / 1M [busy]
Data RAM [0] start address / size 0x3ffc0000 / 256K [busy]
Data RAM [1] start address / size 0x3ff80000 / 256K [busy]
Data ROM start address / size 0x3ff40000 / 256K [busy]
XLMI start address / size 0x3ff00000 / 256K [busy]
Vector configuration
Reset Vector start address / size 0x50000000 / 0x300
Kernel (Stacked) Exception Vector start address / size 0x40000030 / 0x1c
User (Program) Exception Vector start address / size 0x40000050 / 0x1c
Double Exception Vector start address / size 0x40000070 / 0x10
Level 2 Interrupt Vector start address / size 0x40000010 / 0xc
Level 3 Interrupt Vector (NMI vector) start address / size 0x40000020 / 0xc
Relocatable Vectors yes
Selected Static Vector set Primary
Primary Static Vector Group Base Address 0x50000000
Alternate Static Vector Group Base Address 0x40000080
Alternate Reset Vector Address 0x40000080
Default Dynamic Vector Group Base Address (VECBASE) 0x40000000
Target & CAD options
Functional Unit Clock Gating yes
Global Clock Gating yes
Register file implementation block (Latches are deprecated) Flip-flops
Asynchronous Reset no
Software Target Options
Xtensa Tools should use Extended L32R no
Software ABI call0
C Libraries newlib
Compatibility Checking
Generic RTOS compatibility no
Target Linux compatibility no
Variant no
-------------
Т.е. вот это всё есть из китайского утекшего SDK:
Tensilica RC-2010.1 Documentation Index
General
Xtensa Processors RC-2010.1 Release Note
Tensilica Standard Processors RC-2010.1 Release Note
Xtensa Upgrade Guide
Diamond Series Processors Upgrade Guide
Xtensa Development Tools Installation Guide
Summary of Documentation Changes in RC-2010.1
Architecture
Xtensa Instruction Set Architecture (ISA) Reference Manual
HiFi2/EP Audio Engine ISA Reference Manual
ConnX D2 DSP Engine User's Guide
ConnX Vectra LX DSP Engine Guide
Tensilica Instruction Extension (TIE) Language Reference Manual
Tensilica Instruction Extension (TIE) Language User's Guide
Xtensa Processor Extensions Synthesis (XPRES) Compiler User's Guide
Xtensa Processor Interface Protocol Reference Manual
Xtensa Hardware
Xtensa LX3 Microprocessor Data Book
Xtensa 8 Microprocessor Data Book
Xtensa Hardware User's Guide
Tensilica Processors Bus Bridges Guide
Tensilica Bus Designer's Toolkit Guide
Xtensa System Designer's Guide
Tensilica Avnet LX60 (XT-AV60) Board
Tensilica Avnet LX200 (XT-AV200) Board
Standard DSP and Diamond Controllers
Diamond Series Hardware User's Guide
Tensilica 330HiFi Standard DSP Data Book
ConnX 545CK Standard DSP Data Book
Tensilica Diamond Standard Controllers Data Book
Software Tools
Xtensa Software Development Toolkit User's Guide
Tensilica C Application Programmer's Guide
Xtensa C and C++ Compiler User's Guide
Xtensa Instruction Set Simulator (ISS) User's Guide
Xtensa SystemC (XTSC) User's Guide
Xtensa SystemC in the Carbon SoC Designer Environment User's Guide
Xtensa SystemC (XTSC) Reference Manual
Xtensa SystemC (XTSC) Reference Manual (zip of HTML)
Xtensa Modeling Protocol (XTMP) User's Guide
Xtensa Energy Estimator (Xenergy) User's Guide
Xtensa Linker Support Packages (LSPs) Reference Manual
Xtensa Microprocessor Programmer's Guide
Xtensa System Software Reference Manual
Xtensa OSKit Guide
Tensilica On-Chip Debugging Guide
Tensilica Trace Solutions User's Guide
The Red Hat newlib C Library Reference Manual
The Red Hat newlib C Math Library Reference Manual
GNU Assembler User's Guide
GNU Binary Utilities User's Guide
GNU Debugger User's Guide
GNU Linker User's Guide
GNU Profiler User's Guide
Xtensa Co-Simulation Model for Mentor Graphics Seamless User's Guide
Addenda
Xtensa LX3 Data Book Prefetch Addendum
По ld\eagle.rom.addr.v6.ld есть это:
http://df.lth.se/~kongo/esp8266.bin/
